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Error-correcting code memory ECC memory is a type of computer data storage that can detect and correct the most common kinds of internal data corruption. ECC memory is used in most computers where data corruption cannot be tolerated memkrija any circumstances, such as for scientific or financial computing. Typically, ECC memory maintains a memory system immune to single-bit errors: Electrical or magnetic interference inside a computer system can cause a single bit of dynamic random-access memory DRAM to spontaneously flip to the opposite state.

It was initially thought that this was mainly due to alpha particles emitted by contaminants in chip packaging material, but research has shown that the majority of one-off soft errors in DRAM chips occur as a result of background radiationchiefly neutrons from cosmic ray secondaries, which may change the contents of one or more memory cells or interfere with the circuitry used to read or write to them.

As an example, the spacecraft Cassini—Huygenslaunched incontained two identical flight recorders, each with 2. Thanks to built-in EDAC functionality, spacecraft’s engineering telemetry reported the number of correctable single-bit-per-word errors and uncorrectable double-bit-per-word errors.

During the first 2. However, on November 6,during the first month in space, the number of errors increased by more than a factor of four for that single day.

This was attributed to a solar particle event that had been detected by the satellite GOES 9. There was some concern that as DRAM density increases further, and thus memoroja components on chips get smaller, while at the same time operating voltages continue to fall, DRAM memlrija will be affected by such radiation more frequently—since lower-energy particles will be able to change a memory cell’s state.

Recent studies [6] show that single event upsets due to cosmic radiation have been dropping dramatically with process geometry and previous concerns over increasing bit cell error rates are unfounded.

The consequence of a memory error is system-dependent.

Memorija Crucial DDR4 16GB 2666MHz ECC, CT16G4RFS4266

In systems without ECC, an error can lead either to a crash or to corruption of data; in large-scale production sites, memory errors are one of the most common hardware causes of machine crashes. A simulation study showed that, for a web browser, only a small fraction of memory errors caused data corruption, although, as many memory memoriija are intermittent and correlated, the effects of memory errors were greater than would be expected for independent soft errors.

Some tests conclude that the isolation of DRAM memory cells can be circumvented by unintended side effects of specially crafted accesses to adjacent cells. Thus, accessing data stored in DRAM causes memory cell to dddr their charges and interact electrically, as a result of high cell density in modern memory, altering the content of nearby memory rows that actually were not addressed in the original memory access.


This effect is known as row hammerand it has also been used in some privilege escalation computer security exploits. An example of a single-bit error that would be ignored by a system with no error-checking, would mdmorija a machine with parity checking, or would be invisibly corrected by ECC: Several approaches have been developed to deal with unwanted bit-flips, including immunity-aware programmingRAM parity memory, and ECC memory.

This problem can be mitigated by using DRAM modules that include extra memory bits and memory controllers that exploit these bits. These extra bits are used to record parity or to use an error-correcting code ECC. Parity allows the detection of all single-bit errors actually, any odd number dd wrong bits. The most common error correcting code, a single-error correction and double-error detection SECDED Hamming codeallows a single-bit error to be corrected and in the usual configuration, with an extra parity bit double-bit errors to be detected.

Ddf ECC is a more effective version that also corrects for multiple bit errors, including the loss of an drr memory chip. Seymour Cray famously said ” parity is for farmers ” when asked why he left this out of the CDC Many current drr memory controllers, including almost all AMD bit offerings, support ECC, but many motherboards and in particular memoriia using low-end chipsets do not. An ECC-capable memory controller can detect and correct errors of a single bit per bit ” memoeija ” the unit of bus transferand detect but not correct errors of two bits per bit word.

The BIOS in some computers, dvr matched with operating systems such as some versions of LinuxmacOSand Windows[ citation needed ] allows counting of detected and corrected memory errors, in part to help identify failing memory modules before ,emorija problem becomes catastrophic. Error detection and correction EDAC depends on an expectation of the kinds of errors that occur. Implicitly, it is assumed that the failure of each bit in a word of memory is independent, resulting in improbability of two simultaneous errors.

This used to be the case when memory chips were one-bit wide, what was typical in the first half of the s; later developments moved many bits into the same chip.

DRAM memory may provide increased protection against soft errors by relying on error correcting codes.

DDR2 SDRAM – Wikipedia

Such error-correcting memoryknown as ECC or EDAC-protected memory, is particularly desirable for high fault-tolerant applications, such as servers, as well as deep-space applications due to increased radiation.

Some systems also ” scrub ” the memory, by periodically reading all addresses and writing back corrected versions if necessary to remove soft errors. Interleaving allows mdmorija distribution of the effect of a single cosmic ray, potentially upsetting multiple physically neighboring bits across multiple words by associating neighboring bits to different words.

As long as a single event upset SEU does not exceed the error threshold e. Error-correcting memory controllers traditionally use Mwmorija codesalthough some use triple memoriha redundancy TMR.

The latter is preferred because its hardware is faster than that of Hamming error correction scheme.


Many early implementations of ECC memory mask correctable errors, acting “as if” the error never occurred, and only report uncorrectable errors. Modern implementations log both correctable errors CE and uncorrectable errors UE. Some people proactively replace memory modules that jemorija high error rates, in order to reduce the likelihood of uncorrectable error events. As ofthe most common error-correction codes use Hamming or Hsiao codes that provide single bit error correction and double bit error detection SEC-DED.

Early research attempted to minimize the area and delay overheads of ECC circuits. More recent research also attempts to minimize power in addition to minimizing area and delay. If an error is detected, data is recovered from ECC-protected level 2 cache.

Registered, or buffered, memory is not the same as ECC; these strategies perform different functions. It is usual for memory used in servers to be both registered, to allow many memory modules to be used without ddrr problems, and ECC, for data integrity. Memory used in desktop computers is neither, for economy. Ultimately, there is a trade-off between protection against unusual loss of data, and a higher cost. ECC protects against undetected memory data corruption, and is used in computers where such corruption is unacceptable, for example in some scientific and financial computing applications, or in file servers.

ECC also reduces the number of crashes, that are especially unacceptable in multi-user server applications and maximum-availability systems. Most dddr and dvr for less critical application are not designed to support ECC so their prices can be kept lower. ECC memory usually involves a higher price when compared to non-ECC memory, due to additional hardware required for producing ECC memory modules, and due memoruja lower production volumes of ECC memory and associated system hardware.

Motherboards, chipsets and processors that support ECC may also be more expensive. ECC may lower memory performance by around 2—3 percent on some systems, depending on the application and implementation, due to the additional time needed for ECC memory controllers to perform error checking.

From Wikipedia, the free encyclopedia. Retrieved October 20, Swift and Steven M.

Lay summary — ZDNet. Archived from the original on Reliability, Availability, and Serviceability”. Retrieved 15 October Sadler and Daniel J. Primary computer data storage technologies. Delay line memory Selectron tube Williams tube. Bubble memory Drum memory Magnetic-core memory Twistor memory.

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